IoT-VLSI

Course 1. DIGITAL LOGIC DESIGN AND FPGA BASICS
Part A. Logic Design with Verilog
  1. Verilog Basics
    • Introduction to verilog
    • Advantages of using verilog
    • Verilog application areas
    • Abstraction levels
    • Lexical conventions in verilog
    • Data types
    • Port connectivity rules
    • Blocking and non-blocking assignments
    • Types of modelling
    • Task and function
    • Modelling techniques
    • Event timing and delays
  2. Combinational circuit coding
    • Combinational circuits revision
    • Concurrent statements
    • logic gates
    • Adders and substractors
    • Mux and demux
    • Encoders and decoders
    • Comparators
    • Coding of combinational circuits
  3. Finite state machines
    • Finite state machines(mealy, moore)
    • Case statements
    • Parameters
    • Process statement
    • Shift registers
    • Sequence detector and FSM coding with VHDL/verilog

 

Part B. FPGA basics and synthesis
  1. Basics of FPGA ,Xilinx ISE tool flow and implementation
    • Introduction to FPGA and PLD
    • Role of FPGA in VLSI industry
    • FPGA design flow
    • Synthesizable logic design techniques
    • Source code generation with Xilinx ISE
    • Compilation
    • Synthesis
    • I/O Placement
    • Place and route
    • Timing Analysis
    • Bit file generation
    • Synthesizing code on FPGA
    • Synthesizable coding tips and tricks
    • Introduction to Xilinx ISE add-ons
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Course 2. DIGITAL LOGIC DESIGN AND SV BASED VERIFICATION
Part A. Logic Design with Verilog
  1. Verilog Basics
    • Introduction to verilog
    • Advantages of using verilog
    • Verilog application areas
    • Abstraction levels
    • Lexical conventions in verilog
    • Data types
    • Ports and connectivity rules
    • Blocking and non-blocking assignments
    • Types of modelling
    • Task and function
    • Modelling techniques
    • Event,timing and delays
  2. Combinational circuit coding
    • Combinational circuits revision
    • Concurrent statements
    • logic gates
    • Adders and substractors
    • Mux and demux
    • Encoders and decoders
    • Comparators
    • Coding of combinational circuits
  3. Sequential circuit coding
    • Sequential statement(Case,If,while,etc)
    • Procedural blocks(always,initial)
    • Operators
    • Logic and case equality
    • Sequential circuits coding(FFs,counters,registers,etc)
  4. Finite state machines
    • Finite state machines(mealy, moore)
    • Case statements
    • Parameters
    • Process statement
    • Shift registers
    • Sequence detector and FSM coding with verilog

 

Part B. SV based verification
  1. Verification concepts and system verilog
    • Introduction to verification plan and concepts
    • SV based verification environment
    • Understanding functional verification
    • Datatypes
    • Connecting testbench and design
    • Program block
    • Assertions
    • Object oriented programming concepts overview
    • Classes in SV
    • SV constructs
    • Randomization
    • Mailboxes
    • Inheritance
    • Functional verification with SV

Course Project : We guide our interns to get hands on multiple live industrial projects based on latest industrial trends to get experience and develop specialized approach towards digital logic design and SV based verification.

Course 1. ADVANCED FPGA LOGIC DESIGN COURSE
  1. Fundamantals of Digital VLSI design
    • Understanding Digital design concepts
    • Understanding combinational and sequential logic circuits
    • Introduction to Verilog HDL and its use in logic design
  2. Introduction to FPGA
    • Introduction to PLD, CPLD& FPGA
    • FPGA design flow
    • Understanding FPGA architecture in detail
    • ISE design suite tutorial
  3. Hardware coding with verilog
    • Verilog detailed concepts
    • Coding with verilog examples
  4. Advanced synthesis & implementation flow
    • Synthesis options and HDL design analysis
    • Translate,Map,PnR,Bitgen options
    • FPGA programming (JTAG)
    • FPGA and FLASH Programming
    • Static timing analysis(STA) concepts
    • Chipscope for in design analysis
    • iMPACT
  5. Timing constraints
    • Different path and I/O constraints
    • Clock region specification
    • Viewing and analyzing timing
  6. Advanced FPGA timing closure flow
    • Typical FPGA timing closure flow
    • RTL coding techniques
    • Creating UCF constraints
    • Xilinx Coregen (add-on)
    • Xilinx planahead (add-on)
    • Floorplanning, area planning and I/O planning
  7. Advanced FPGA implementation for higher performance
    • Hierarchial synthesis
    • Macro placement
    • Critical path optimization with FPGA editor
    • Re-entrant routing
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Course 2. RTL VERIFICATION WITH SYSTEM VERILOG AND UVM
  1. Understanding verification concepts
    • Introduction to verification plan and process
    • Testing at different levels
    • Basic test bench
    • Directed testing
    • Random testing
    • Constrained random stimulus
    • Functional coverage
    • Test bench components
  2. Data types and Constructs
    • The logic types
    • 2-state data types
    • Types of arrays
    • Array methods
    • Creating new types with ‘typedef’
    • Creating user-defined structures
    • Packages
  3. Object oriented programming
    • Basic OOP concepts
    • Using objects
    • Methods
    • Inheritance
    • Abstraction
    • Encapsulation
    • Polymorphismd
  4. Connecting the test bench and design
    • Communication b/w test bench& DUT
    • Interface construct
    • Interface Signal Drive
    • Modports
    • Clocking blocks
    • Program blockd
  5. Randomization
    • Randomization in system verilog
    • Systemverilog constrained random verification
    • Constraints
    • Randsequence
    • Randcase
  6. Threads and Interprocess communications
    • Working with threads
    • Disabling threads
    • Events
    • Mailboxes
  7. Assertion
    • Use of assertions in SV based
      environment
    • System functions
    • Immediate assertions
    • Concurrent assertions
  8. Functional coverage
    • Functional coverage features of SV(Introduction)
    • Coverage types
    • Covergroup
    • Coverage points
    • Different types of
  9. UVM methodology for SV based verification
    • Introduction to UVM
    • Advantages of UVM over SV ( UVM – SV comparison)
    • Constrained random testbench
    • Understanding the need of methodology
    • Factory registration
    • Factory overrides
    • UVM class hierarchy
    • TLM
    • Phase execution
    • UVM classes
  10. UVM environment configuration
    • Configuration
    • Config db
    • Configuring sequences
    • Introduction to macros
  11. Analysis techniques
    • Analysis
    • Analysis connections
    • Monitoring components
    • Scoreboards
  12. UVM reporting and End of test mechanism
    • UVM report info
    • UVM report warning
    • UVM report error
    • UVM report fatal
    • UVM verbosity
    • End of test
    • Objections
    • Major UVM transcript commands
  13. Test automation based on scripting language
    • Introduction to scripting concept
    • Linux
    • tcl/tk
    • make file and make